ACE25C512G Datasheet, PDF (7/37 Pages) ACE Technology Co., LTD. – Uniform Sector Dual and Quad Serial Flash

ACE25C512G
Uniform Sector Dual and Quad Serial Flash
SEC, TB, BP2, BP1, BP0 bits
The Block Protect (SEC, TB, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase commands. These bits are written with the Write
Status Register (WRSR) command. When the Block Protect (SEC, TB, BP2, BP1, BP0) bits are set to
1, the relevant memory area (as defined in Table1).becomes protected against Page Program (PP),
Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (SEC, TB, BP2, BP1, BP0)
bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE)
command is executed, if the Block Protect (BP2, BP1, BP0) bits are “000” when CMP=0, or “110/111”
when CMP=1.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status
register. The SRP bits control the method of write protection: software protection, hardware protection,
power supply lock-down or one time programmable protection.
SRP1 SRP0 #WP Status Register
Description
0
0
X
Software
Protected
The Status Register can be written to after a
Write Enable command, WEL=1.(Default)
0
1
0
Hardware
Protected
WP#=0, the Status Register locked and can not be written to
Hardware
WP#=1, the Status Register is unlocked and can be written
0
1
1
Unprotected
to after a Write Enable command, WEL=1
1
0
X
Power Supply Status Register is protected and can not be written to again
Lock- Down(1)
until the next Power-Down, Power-Up cycle
1
1
X
One Time
Program (2)
Status Register is permanently protected and can not be
written to
Note:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. The One time Program feature is available upon special order. Please contact ACE for details.
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad
operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE
pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during
standard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or
ground)
LB3/LB2/LB1 bit.
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the
write protect control and status to the Security Registers. The default state of LB is 0, the security
registers are unlocked. LB can be set to 1 individually using the Write Register instruction. LB is One
Time Programmable, once it’s set to 1, the Security Registers will become read-only permanently.
LB0 is reserved, LB3/2/1 for Security Registers 3:1.
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