ACE25C512G Datasheet, PDF (6/37 Pages) ACE Technology Co., LTD. – Uniform Sector Dual and Quad Serial Flash

ACE25C512G
Uniform Sector Dual and Quad Serial Flash
Table1.0 ACE25C512G Protected area size
Status Register Content
Memory Content
SEC TB BP2 BP1 BP0 Blocks
Addresses
Density
0 XX
0
0 NONE
NONE
NONE
0 XX
0
1
0
000000H-00FFFFH
64KB
0 XX
1
X
0
000000H-00FFFFH
64KB
1X0
0
0 NONE
NONE
NONE
100
0
1
0
00F000H-00FFFFH
4KB
100
1
0
0
00E000H-00FFFFH
8KB
100
1
1
0
00C000H-00FFFFH 16KB
101
0
X
0
008000H-00FFFFH
32KB
101
1
0
0
008000H-00FFFFH
32KB
110
0
1
0
000000H-000FFFH
4KB
110
1
0
0
000000H-001FFFH
8KB
110
1
1
0
000000H-003FFFH
16KB
111
0
X
0
000000H-007FFFH
32KB
111
1
0
0
000000H-007FFFH
32KB
1X1
1
1
0
000000H-000FFFH
64KB
Portion
NONE
ALL
ALL
NONE
Top Block
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
ALL
Status Register
S15
S14
SUS
CMP
S13
S12
S11
LB3
LB2
LB1
S10
Reserved
S9
S8
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
SEC
TB
BP2
BP1
BP0
WEL
W1P
The status and control bits of the Status Register are as follows:
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status
register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status
register progress, when WIP bit sets 0, means the device is not in program/erase/write status register
progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to
1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no
Write Status Register, Program or Erase command is accepted.
VER 1.5 6