ACE25C512G Datasheet, PDF (21/37 Pages) ACE Technology Co., LTD. – Uniform Sector Dual and Quad Serial Flash

ACE25C512G
Uniform Sector Dual and Quad Serial Flash
Figure17. 64KB Block Erase Sequence Diagram
Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip
Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data
Input (SI). CS# must be driven Low for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low sending Chip Erase command CS# goes high.
The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the
command code has been latched in, otherwise the Chip Erase command is not executed. As soon as
CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the
Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is
0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset. The Chip Erase (CE) command is executed only if the Block Protect (BP2,
BP1, BP0) bits are “000” when CMP=0, or “110/111” when CMP=1. The Chip Erase (CE) command is
ignored if one or more sectors are protected.
Figure18. Chip Erase Sequence Diagram
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