ACE25C512G Datasheet, PDF (4/37 Pages) ACE Technology Co., LTD. – Uniform Sector Dual and Quad Serial Flash

ACE25C512G
Uniform Sector Dual and Quad Serial Flash
Ordering information
ACE25C512G XX + X H - X
Null : Commercial (0~70℃)
I: Industrial (-40~85℃)
Halogen-free
U: Tube
T: Tape and Reel
Pb - free
DP: DIP-8
FM: SOP-8
Uniform Block Sector Architecture
TM: TSSOP-8
ACE25C512G 64K Bytes Block Sector Architecture
Block
Sector
Address range
15
00F000H
00FFFFH
1
….
….
….
8
008000H
008FFFH
7
007000H
007FFFH
0
….
….
….
0
000000H
000FFFH
Device Operation
SPI Mode
Standard SPI
The ACE25C512G features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are
supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of
SCLK.
Dual SPI
The ACE25C512G supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual
I/O Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from
the device at two times the rate of the standard SPI. When using the Dual SPI command the SI and
SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The ACE25C512G supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad
I/O Fast Read”(6BH, EBH) commands. These commands allow data to be transferred to or from the
device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO
pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3.
Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status Register to be set.
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