ACE25Q512G Datasheet, PDF (33/42 Pages) ACE Technology Co., LTD. – 512K BIT SPI NOR FLASH Memory Series

ACE25Q512G
512K BIT SPI NOR FLASH Memory Series
Chip Erase (60/C7H)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A
Write Enable instruction must be executed before the device will accept the Chip Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and
shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure
29.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip
Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction
will commence for a time duration of tCE. While the Chip Erase cycle is in progress, theself-timed
Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the
Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In
Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A 64KB Block
Erase instruction applied to a block which is protected by the Block Protect (SEC, TB, BP2, BP1, BP0)
bits (see Table 6) is not executed.
Figure 29 64KB Block Erase Sequence Diagram
Figure 29
Erase / Program Suspend (75H)
The Erase/Program Suspend instruction allows the system to interrupt a Sector or Block Erase
operation, then read from or program data to any other sector. The Erase/Program Suspend
instruction also allows the system to interrupt a Page Program operation and then read from any other
page or erase any other sector or block. The Erase/Program Suspend instruction sequence
is shown in Figure 30.
The Write Status Registers instruction (01h) and Erase instructions (20h, D8h, C7h, 60h, 44h) are
not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If
written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Registers
instruction (01h), and Program instructions (02h, 42h) are not allowed during Program Suspend. Program
Suspend is valid only during the Page Program operation.
Figure 30 Erase/Program Suspend Command Sequence
Figure 30
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