ACE25Q512G Datasheet, PDF (17/42 Pages) ACE Technology Co., LTD. – 512K BIT SPI NOR FLASH Memory Series

ACE25Q512G
512K BIT SPI NOR FLASH Memory Series
Fast Read (0BH)
See Figure 8, the Read Data Bytes at Higher Speed (Fast Read) instruction is for quickly reading
data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in
during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each
bit being shifted out, at a Max frequency fc, during the falling edge of SCLK. The first byte addressed
can be at any location. The address is automatically incremented to the next higher address after
each byte of data is shifted out.
Figure 8 Fast Read Sequence Diagram
Figure 8
Dual Output Fast Read (3BH)
See Figure 9, the Dual Output Fast Read instruction is followed by 3-byte address (A23-A0) and a
dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are
shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
Figure 9 Dual Output Fast Read Sequence Diagram
Figure 9
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