ACE25Q512G Datasheet, PDF (15/42 Pages) ACE Technology Co., LTD. – 512K BIT SPI NOR FLASH Memory Series

ACE25Q512G
512K BIT SPI NOR FLASH Memory Series
Read Status Register (05H or 35H)
See Figure 4, the Read Status Register (RDSR) instruction is for reading the Status Register. The
Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the Write in
Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status
Register continuously. For instruction code “05H”, the SO will output Status Register bits S7~S0. The
instruction code “35H”, the SO will output Status Register bits S15~S8.
Figure 4. Read Status Register Sequence Diagram
Figure 4
Write Status Register (01H)
See Figure 5, the Write Status Register instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable instruction must previously have been executed.
After the Write Enable instruction has been decoded and executed, the device sets the Write Enable
Latch (WEL).
The Write Status Register instruction has no effect on S15, S1 and S0 of the Status Register. /CS
must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write
Status Register instruction is not executed. If /CS is driven high after eighth bit of the data byte, the
QE and SRP1 bits will be cleared to 0. As soon as /CS is driven high, the self-timed Write Status
Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress,
the Status Register may still be read to check the value of the Write in Progress (WIP) bit. The Write in
Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch is reset.
The Write Status Register instruction allows the user to change the values of the Block Protect
(SEC, TB, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as
defined in Table 3. The Write Status Register instruction also allows the user to set or reset the Status
Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (/WP) signal. The Status
Register Protect (SRP1 and SRP0) bits and Write Protect (/WP) signal allow the device to be put in
the Hardware Protected Mode. The Write Status Register instruction is not executed once the
Hardware Protected Mode is entered.
Figure 5 Write Status Register Sequence Diagram
Figure 5
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