ACE25C320G Datasheet, PDF (22/37 Pages) ACE Technology Co., LTD. – Uniform SECTOR Dual and Quad Serial Flash

ACE25C320G
Uniform SECTOR Dual and Quad Serial Flash
Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip
Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data
Input (SI). CS# must be driven Low for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low sending Chip Erase command CS# goes high.
The command sequence is shown in Figure18. CS# must be driven high after the eighth bit of the
command code has been latched in, otherwise the Chip Erase command is not executed. As soon as
CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the
Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is
0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset. The Chip Erase (CE) command is executed only if the Block Protect (BP2,
BP1, BP0) bits are “000” when CMP=0, or “110/111” when CMP=1. The Chip Erase (CE) command is
ignored if one or more sectors are protected.
Figure18. Chip Erase Sequence Diagram
Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest
consumption mode (the Deep Power-Down Mode). It can also be used as an extra software
protection mechanism, while the device is not in active use, since in this mode, the device ignores all
Write, Program and Erase commands. Driving CS# high deselects the device, and puts the device in
the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the Deep
Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep
Power-Down (DP) command. Once the device has entered the Deep Power-Down Mode, all
commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI)
command. This releases the device from this mode. The Release from Deep Power-Down and Read
Device ID (RDI) command also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up
in the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed
by the command code on SI. CS# must be driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low sending Deep Power-Down command
CS# goes high. The command sequence is shown in Figure19. CS# must be driven high after the
eighth bit of the command code has been latched in; otherwise the Deep Power-Down (DP)
command is not executed. As soon as CS# is driven high, it requires a delay of tDP before the
supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep
Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in progress.
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