THS6182_08 Datasheet, PDF (21/35 Pages) Texas Instruments – LOW-POWER DISSIPATION ADSL LINE DRIVER

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THS6182
SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007
APPLICATION INFORMATION (continued)
0.4953
0.3721
0.1905
Pad size
24 x (0.3048 x 0.762) mm
0.1905
2.2987
0.4953
4.9022
0.3641
3.302
5.9182
PowerPAD and Via layout
(Pad size 3.65 mm x 2.65 mm ,
9 Vias with diameter = 0.254 mm)
0.682
1.143
2.65
0.563
0.762
3.65
Vias should go through the board connecting the top layer PowerPAD to any and all
ground planes. The larger the ground plane, the more area to distribute the heat.
Solder resist should be used on the bottom side ground plane to prevent wicking of
the solder through the vias during the reflow process.
Figure 74. Suggested PCB Layout
The actual thermal performance achieved with the THS6182 in the 20-pin DWP PowerPAD package depends on
the application. In the previous example, if the size of the internal ground plane is approximately 3 inches × 3
inches, then the expected thermal coefficient, Θ_JA, is about 21.5°C/W. (See the Package Dissipation Ratings
Table for all other package metrics.) For a given Θ_JA, the maximum power dissipation is calculated by the
following formula:
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