THS6182_08 Datasheet, PDF (19/35 Pages) Texas Instruments – LOW-POWER DISSIPATION ADSL LINE DRIVER

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THS6182
SLLS544H – SEPTEMBER 2002 – REVISED JUNE 2007
APPLICATION INFORMATION (continued)
1 kΩ
Input
1 kΩ
_
THS6182
+
2Ω
Output
C_LOAD
Figure 72. Driving a Capacitive Load
PCB DESIGN CONSIDERATIONS
Proper PCB design techniques in two areas are important to assure proper operation of the THS6182. These
areas are high-speed layout techniques and thermal-management techniques. Because the THS6182 is a
high-speed part, the following guidelines are recommended.
• Ground plane - It is essential that a ground plane be used on the board to provide all components with a low
inductive ground connection. Although a ground connection directly to a terminal of the THS6012 is not
necessarily required, it is recommended that the thermal pad of the package be tied to ground. This serves
two functions. It provides a low inductive ground to the device substrate to minimize internal crosstalk and it
provides the path for heat removal. Note that the BiCom process is a SOI process and thus, the substrate is
isolated from the active circuitry.
• Input stray capacitance - To minimize potential problems with amplifier oscillation, the capacitance at the
inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input
must be as short as possible, the ground plane should be removed under any etch runs connected to the
inverting input, and external components should be placed as close as possible to the inverting input. This is
especially true in the noninverting configuration.
• Proper power supply decoupling - Use a minimum of a 6.8-µF tantalum capacitor in parallel with a 0.1-µF
ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several
amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply
terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the
supply terminal. As this distance increases, the inductance in the connecting etch makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power terminal
and the ceramic capacitors.
• For a differential configuration as shown in Figure 1, it is recommended that a 0.1-µF or 1-µF capacitor be
added across the power supplies (from V_CC+ to V_CC- ) as close as possible to the THS6182. This allows for
differential currents to flow properly, signficantly reducing even-order harmonic distortion. The 0.1-µF
capacitors to ground should also be used as previously stipulated.
Because of its power dissipation, proper thermal management of the THS6182 is required. Although there are
many ways to properly heatsink this device, the following steps illustrate one recommended approach for a
multilayer PCB with an internal ground plane utilizing the 20 pin DWP PowerPAD package.
1. Prepare the PCB with a top side etch pattern as shown in Figure 73. There should be etch for the leads
as well as etch for the thermal pad.
2. Place 18 holes in the area of the thermal pad. These holes should be 13 mils in diameter. They are kept
small so that solder wicking through the holes is not a problem during reflow.
3. It is recommended, but not required, to place six more holes under the package, but outside the thermal
pad area. These holes are 25 mils in diameter. They may be larger because they are not in the area to be
soldered so that wicking is not a problem.
4. Connect all 24 holes, the 18 within the thermal pad area and the 6 outside the pad area, to the internal
ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the
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