IND16305 Datasheet, PDF (4/7 Pages) Integral Corp. – 40-BIT AC-PDP DRIVER

IND16305
TRUTH TABLE 1 (Shift Register Block)
R/L CLK A
B
Shift Register
H
↑
Input Output Right shift execution
H
H or L
Hold
L
↑
Output Input Left shift execution
L
H or L
Hold
TRUTH TABLE 2 (Latch Block)
STB
Operation
H
Data immediately prior to STB becoming H is held
L
Shift register data is output
TRUTH TABLE 3 (Driver Block)
DATA
BLK
PC
On
Remarks
H
L
L
H
L
L
L
L
H
L
H
L
L
L
H
H
Ð¥
H
L
H
All outputs H
Ð¥
H
H
L
All outputs L
H→: High level
L→: Low level
Х→: H or L
DATA: Data input to A (B)
Caution To prevent latch up breakdown, the power should be turned on in the order VDD1, logic signal, VDD2.
It should be turned off in the opposite order.
TIMING CHART
( ): When R/L=L
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