IND16305 Datasheet, PDF (2/7 Pages) Integral Corp. – 40-BIT AC-PDP DRIVER

IND16305
PIN CONFIGURATION (Top View)
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
O16
O17
O18
O19
O20
VDD2
VSS2
VSS2
VSS1
1
64
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
47
19
46
20
45
21
44
22
43
23
42
24
41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
O40
O38
O37
O36
O35
O34
O33
O32
O31
O30
O29
O28
O27
O26
O25
O24
O23
O22
O21
VDD2
VSS2
VSS2
VSS1
• Ensure that the VDD1, VDD2, VSS1 and VSS2 pins are all used, and that VSS1 and VSS2 are used at the same potential
(connect at same point near IC).
• Pin 33 is connected to the lead frame, and must therefore be left open.
DESCRIPTION OF PINS
Pin Symbol
Pin Name
Pin No.
Description
BLK
Output blank input
37
A
RIGHT data input/output
30
See truth table
Serial data input/output* When R/L = H
A: Input B:Output
B
LEFT data input/output
35
CLK
Clock input
31
STB
Latch enable input
36
R/L
Shift direction control input
25
When R/L = L A: Output B: Input
Shift executed on rise
H: Latch, L: Data-through
H: Right shift modeA→O1 ···O40→B
L : Left shift mode B→O40→···O1 A
CLR
Clear input
32
L: Shift register ALL L
PC
Polarity reversal input
27
See truth table
O1 to O40
High withstand voltage outputs
1 to 20
200 V, 400 mA max.
45 to 64
VDD1
Logic block power supply
26, 39
5 V ± 10 %
VDD2
Driver block power supply
21, 44
30 V to 180 V
VSS1
Logic block ground
24, 41
Connect to system GND
VSS2
Driver block ground
22, 23, 42, 43
Connect to system GND at same point.
NC
Unused pins
28, 29, 33,
Non-connection
34, 38, 40
Ensure that pin 33 is left open.
* Data resulting from inversion of the data input is input to the shift register, and data resulting from inversion of the shift
register data is output to the output.
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