IND16305 Datasheet, PDF (3/7 Pages) Integral Corp. – 40-BIT AC-PDP DRIVER

IND16305
ELECTRICAL SPECIFICATIONS (Ta = 25 ^oC, VDD1 = 4.5 to 5.5 V, VDD2 = 180 V, VSS1 = VSS2 = 0 V)
PARAMETER
SYMBOL MIN.
MAX.
UNIT TEST CONDITIONS
Output voltage high
Output voltage low
Output voltage high
Output voltage low
Input current
V_OH1
V_OL1
V_OH21
V_OH22
V_OL21
V_OL22
I_I
0.9 · V_DD1
V
0.1 · V_DD1 V
160
V
140
V
20
V
40
V
±1
uA
Logic I_OH = –1 mA
Logic I_OL = 1 mA
O₁ to O₄₀, I_OH = –150 mA
O₁ to O₄₀, I_OH = –300 mA
O₁ to O₄₀, I_OL = 150 mA
O₁ to O₄₀, I_OL = 300 mA
V_I = V_DD1 or V_SS1
Input voltage high
V_IH
Input voltage low
V_IL
Static comsumption current I_DD1
I_DD1
I_DD2
I_DD2
0.8 · V_DD1
V
0.2 · V_DD1 V
100
uA
10
uA
1
mA
100
uA
Logic Ta = –40 to +85 ^oC
Logic Ta = 25 ^oC
Driver Ta = –40 to +85 ^oC
Driver Ta = 25 ^oC
SWITCHING CHARACTERISTICS (Ta = 25 ^oC, VDD1 = 5 V, VDD2 = 180 V, Logic CL = 15 pF, Driver CL = 50
pF)
PARAMETER
SYMBOL MIN. MAX. UNIT TEST CONDITIONS
Transmission delay time t_PHL1
120
ns
CLK →A/B
t_PLH1
t_PLH2
120
ns
120
ns
CLR →A/B
t_PHL3
200
ns
CLK →O1 to O40
t_PLH3
t_PHL4
200
ns
200
ns
STB →O1 to O40
t_PLH4
t_PHL5
200
ns
220
ns
BLK →O1 to O40
t_PLH5
t_PHL6
220
ns
220
ns
PC →O1 to O40
t_PLH6
220
ns
Rise time
t_TLH
100
ns
O1 to O40
Fall time
t_THL
100
ns
O1 to O40
Maximum clock frequency f_max.
15
MHz Duty = 50 %
(DATA)
Input capacitance
C_I
15
pF
REQUIRED TIMING CONDITIONS (Ta = –40 to +85 ^oC, VDD1 = 4.5 to 5.5 V)
PARAMETER
SYMBOL MIN. MAX. UNIT TEST CONDITIONS
Clock pulse width
PW_CLK
30
Strobe pulse width
PW_STB
60
Blank pulse width
PW_BLK
200
PC pulse width
PW_PC
300
Clear pulse width
PW_CLR
120
Data setup time
t_SETUP
20
Data hold time
t_HOLD
5
Clock-strobe time
t_CLK-STB
120
ns
ns
ns
ns
ns
ns
ns
ns
CLK ↑→STB ↑
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