IC61C256AH Datasheet, PDF (7/9 Pages) Integrated Circuit Solution Inc – 32K x 8 HIGH-SPEED CMOS STATIC RAM

IC61C256AH
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
Symbol Parameter
-10
-12
-15
-20
-25
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
tWC Write Cycle Time
tSCE CE to Write End
10 — 12 — 15 — 20 — 25 —
ns
9 — 10 — 10 — 13 — 15 —
ns
tAW Address Setup Time
to Write End
9 — 10 — 12 — 15 — 20 —
ns
tHA Address Hold
from Write End
0— 0— 0— 0— 0—
ns
tSA Address Setup Time
tPWE⁽⁴⁾ WE Pulse Width
0— 0— 0— 0— 0—
ns
8 — 8 — 10 — 13 — 15 —
ns
tSD Data Setup to Write End
7 — 7 — 9 — 10 — 12 —
ns
tHD
tHZWE⁽²⁾
tLZWE
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
0— 0— 0— 0— 0—
ns
— 6 — 6 — 7 — 8 — 10
ns
0— 0— 0— 0— 0—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled) ^{(1,2 )}
t WC
ADDRESS
CE
WE
DOUT
DIN
VALID ADDRESS
t SA
t SCE
t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
Integrated Circuit Solution Inc.
7
AHSR010-0D 4/19/2002