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U62H64 Datasheet, PDF (7/9 Pages) Zentrum Mikroelektronik Dresden AG – AUTOMOTIVE FAST 8K X 8 SRAM
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Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH, Ai-controlled)
Ai
DQi
Output
Previous Data Valid
tv(A)
tcR
Addresses Valid
ta(A)
Output Data Valid
U62H64
Read Cycle 2 (during Read cycle: W = VIH, G-, E1- or E2-controlled)
Ai
E1
E2
G
DQi
Output
ICC(OP)
ICC(SB)
tsu(A)
tsu(A)
tcR
Addresses Valid
ta(E)
ten(E)
ta(E)
ten(E)
ta(G)
High-Z
ten(G)
tPU*
50 %
tdis(E)
tdis(E)
tdis(G)
Output Data Valid
tPD*
50 %
* The same applies to E1
Write Cycle 1 (W-controlled)
Ai
E1
E2
W
DQi
Input
DQi
Output
G
tcW
Addresses Valid
tsu(E)
th(A)
tsu(A)
tsu(E)
tw(W)
tdis(W)
tsu(D)
th(D)
Input Data Valid
High-Z
ten(W)
April 20, 2004
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