U62H64 Datasheet, PDF (5/9 Pages) Zentrum Mikroelektronik Dresden AG – AUTOMOTIVE FAST 8K X 8 SRAM

U62H64
Switching Characteristics
Time to Output in Low-Z from
E1 LOW or E2 HIGH
G LOW
W HIGH
Cycle Time
Write Cycle Time
Read Cycle Time
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
Data Hold Time
Address Hold from End of Write
Output Hold Time from Address Change
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
E1 LOW or E2 HIGH to Power-Up
E1 HIGH or E2 LOW to Power-Down
Symbol
Alt.
IEC
t_LZCE
t_LZOE
t_LZWE
t_WC
t_RC
t_ACE
t_OE
t_AA
t_WP
t_CW
t_AS
t_CW
t_WP
t_DS
t_DH
t_AH
t_OH
t_HZCE
t_HZWE
t_HZOE
t_PU
t_PD
t_en(E)
t_en(G)
t_en(W)
t_cW
t_cR
t_a(E)
t_a(G)
t_a(A)
t_w(W)
t_w(E)
t_su(A)
t_su(E)
t_su(W)
t_su(D)
t_h(D)
t_h(A)
t_v(A)
t_dis(E)
t_dis(W)
t_dis(G)
Min.
5
0
0
35
35
20
25
0
25
20
15
0
0
5
0
Unit
Max.
ns
ns
ns
ns
ns
35
ns
15
ns
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
ns
15
ns
12
ns
ns
35
ns
Data Retention Mode E1-Controlled
Data Retention Mode E2-Controlled
4.5 V
2.2 V
t_DR
0V
V_CC(DR) ≥ 2 V
Data Retention
V_CC
2.2 V
t_rec
E1
V_E2(DR) ≥ V_CC(DR) - 0.2 V or V_E2(DR) ≤ 0.2 V
V_CC(DR) - 0.2 V ≤ V_E1(DR) ≤ V_CC(DR) + 0.3 V
4.5 V
t_DR
0.8 V
V_CC(DR) ≥ 2 V
Data Retention ^trec
V_CC
E2
0.8 V
0V
V_E1(DR) ≥ V_CC(DR) - 0.2 V or V_E1(DR) ≤ 0.2 V
V_E2(DR) ≤ 0.2 V
April 20, 2004
Chip Deselect to Data Retention Time t_DR:
Operating Recovery Time at V_CC(DR)
t_rec:
min 0 ns
min t_cR
5