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U6264B Datasheet, PDF (7/9 Pages) Zentrum Mikroelektronik Dresden AG – STANDARD 5K X 8 SRAM
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Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH)
Ai
DQi
Output
Previous Data Valid
tv(A)
tcR
Addresses Valid
ta(A)
Output Data Valid
U6264B
Read Cycle 2 (during Read cycle: W = VIH)
Ai
E1
E2
G
DQi
Output
tsu(A)
tsu(A)
High-Z
tcR
Addresses Valid
ta(E)
tt(QX)
ta(E)
tt(QX)
ta(G)
tt(QX)
tdis(E)
tdis(E)
tdis(G)
Output Data Valid
Write Cycle 1 (W-controlled)
Ai
E1
E2
W
DQi
Input
DQi
Output
G
tcW
Addresses Valid
tsu(E)
th(A)
tsu(A)
tsu(E)
tw(W)
tdis(W)
tsu(D)
th(D)
Input Data Valid
High-Z
tt(QX)
April 20, 2004
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