U6264B Datasheet, PDF (2/9 Pages) Zentrum Mikroelektronik Dresden AG – STANDARD 5K X 8 SRAM

U6264B
Block Diagram
A4
A5
A6
A7
A8
A9
A11
A12
A0
A1
A2
A3
A10
Address
Change
Detector
E2
1
E1
Memory Cell
Array
256 Rows x
256 Columns
Sense Amplifier/
Write Control Logic
Clock
Generator
V_CC V_SS
WG
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Truth Table
Operating Mode
Standby/not selected
Internal Read
Read
Write
* ^{H or L}
E1
E2
W
G
*
L
*
*
H
*
*
*
L
H
H
H
L
H
H
L
L
H
L
*
DQ0 - DQ7
High-Z
High-Z
High-Z
Data Outputs Low-Z
Data Inputs High-Z
2
April 20, 2004