U6264B Datasheet, PDF (5/9 Pages) Zentrum Mikroelektronik Dresden AG – STANDARD 5K X 8 SRAM

Switching Characteristics
Time to Output in Low-Z
Cycle Time
Write Cycle Time
Read Cycle Time
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
Data Hold Time
Address Hold from End of Write
Output Hold Time from Address Change
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
Symbol
Alt.
IEC
t_LZ
t_t(QX)
t_WC
t_cW
t_RC
t_cR
t_ACE
t_OE
t_AA
t_a(E)
t_a(G)
t_a(A)
t_WP
t_w(W)
t_CW
t_w(E)
t_AS
t_CW
t_WP
t_DS
t_DH
t_AH
t_OH
t_HZCE
t_HZWE
t_HZOE
t_su(A)
t_su(E)
t_su(W)
t_su(D)
t_h(D)
t_h(A)
t_v(A)
t_dis(E)
t_dis(W)
t_dis(G)
Min.
5
70
70
-
-
-
50
65
0
65
50
35
0
0
5
0
0
0
U6264B
Max.
Unit
10
ns
ns
ns
70
ns
40
ns
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
ns
30
ns
25
ns
Data Retention Mode E1-Controlled
Data Retention Mode E2-Controlled
4.5 V
2.2 V
t_DR
0V
V_CC(DR) ≥ 2 V
Data Retention
V_CC
4.5 V
2.2 V
t_rec
E1
t_DR
0.8 V
0V
V_E2(DR) ≥ V_CC(DR) - 0.2 V or V_E2(DR) ≤ 0.2 V
V_CC(DR) - 0.2 V ≤ V_E1(DR) ≤ V_CC(DR) + 0.3 V
V_CC(DR) ≥ 2 V
Data Retention
V_E2(DR) ≤ 0.2 V
V_CC
E2
t_rec
0.8 V
April 20, 2004
Chip Deselect to Data Retention Time t_DR :
Operating Recovery Time
t_rec :
min 0 ns
min t_cR
5