Z8018X Datasheet, PDF (88/326 Pages) Zilog, Inc. – Family MPU

Z 8018x Fam ily
M PU Us e r M anual
73
1. DMAC operation is suspended by the clearing of the DME (DMA
Main Enable) bit in DCNTL.
2. The PC is pushed onto the stack.
3. The contents of IEF1 are copied to IEF2. This saves the interrupt
reception state that existed prior to NMI.
4. IEF1 is cleared to 0. This disables all external and internal maskable
interrupts (that is, all interrupts except NMI and TRAP).
5. Execution commences at logical address 0066H.
The last instruction of an NMI service routine must be RETN (Return
from Non-maskable Interrupt). This restores the stacked PC, allowing the
interrupted program to continue. Furthermore, RETN causes IEF2 to be
copied to IEF1, restoring the interrupt reception state that existed prior to
NMI.
Note:
NMI, because it can be accepted during Z8X180 on-chip
DMAC operation, can be used to externally interrupt DMA
transfer. The NMI service routine can reactivate or abort the
DMAC operation as required by the application.
For NMI, take special care to insure that interrupt inputs do not overrun
the NMI service routine. Unlimited NMI inputs without a corresponding
number of RETN instructions eventually cause stack overflow.
Figure 34 depicts the use of NMI and RETN while Figure 35 details NMI
response timing. NMI is edge sensitive and the internally latched NMI
falling edge is held until it is sampled. If the falling edge of NMI is
latched before the falling edge of the clock state prior to T3 or T1 in the
last machine cycle, the internally latched NMI is sampled at the falling
edge of the clock state prior to T3 or T1 in the last machine cycle and
NMI acknowledge cycle begins at the end of the current machine cycle.
UM005001-ZMP0400