Z8018X Datasheet, PDF (146/326 Pages) Zilog, Inc. – Family MPU

Z 8018x Fam ily
M PU Us e r M anual
131
Table 17. Data Formats
MOD2 MOD1 MOD0 Data Format
0
0
0
Start + 7 bit data + 1 stop
0
0
1
Start + 7 bit date + 2 Stop
0
1
0
Start + 7 bit data + parity + 1 stop
0
1
1
Start + 7 bit data + parity + 2 stop
1
0
0
Start + 8 bit data + 1 stop
1
0
1
Start + 8 bit data + 2 stop
1
1
0
Start + 8 bit data + parity + 1 stop
1
1
1
Start + 8 bit date + parity + 2 stop
ASCI Control Register B0, 1 (CNTLB0, 1)
Each ASCI channel control register B configures multiprocessor mode,
parity and baud rate selection.
UM005001-ZMP0400