Z86L82 Datasheet, PDF (66/80 Pages) Maxim Integrated Products – 28-Pin Low-Voltage IR Microcontrollers

Z86L82/85/88
28-Pin Low-Voltage IR Microcontrollers
59
Port Configuration Register (PCON)
The PCON register configures the comparator output on Port 3. It is located in the
expanded register 2 at Bank F, location 00, as shown in Figure 45.
PCON (FH) 00H
D7 D6 D5 D4 D3 D2 D1 D0
*Default setting after reset
Comparator Output Port 3
0 P34, P37, Standard Output*
1 P34, P37, Comparator Output
Reserved (must be 1)
Port 0
0 = Open-drain
1 = Push-pull*
Reserved (must be 1)
Figure 45. Port Configuration Register (PCON)—Write Only
Comparator Output Port 3 (D0)
Bit 0 controls the comparator used in Port 3. A 1 in this location brings the compar-
ator outputs to P34 and P37, and a 0 releases the port to its standard (/O configu-
ration.
Port 0 Output Mode (D2)
Bit 2 controls the output mode of Port 0. A 1 in this location set the output to push-
pull, and a 0 sets the output to open-drain.
Stop-Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of Stop-
Mode Recovery (Figure 46). All bits are write only except bit 7, which is read only.
Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or a high level at the XOR-
gate input is required from the recovery source. Bit 5 controls the reset delay after
recovery. Bits D2, D3, and D4, or the SMR register specify the source of the Stop-
Mode Recovery signal. Bit D0 determines if SCLK/TCLK (shown in Figure 47) are
divided by 16 or not. The SMR is located in Bank F of the Expanded Register
Group at address 0BH.
PS009007-1202