Z87001 Datasheet, PDF (5/51 Pages) Zilog, Inc. – ROMless Spread Spectrum Cordless Phone Controller

Zilog
No
1
2,141
3
4,144
5
6
7,9,11,13,15,17,19,
21,23,25,27,29,31,
136,138,140
8,12,14,16,20,22,24,
28,30,32,36,37,39,
41,44,46
10,26,43,60,77,88,
109,128
18,34,51,68,86,102,
116,131
33,35,38,40,42,45,
47,49,52,54,56,59,
61,63,66,69
48,50,53,55,57,58,
62,64,65,67,70,72,
73,75,79,80
71,74,76,78,81,83,
85,89,91,93,96,98,
100,103,105,107
82,84
87
90
92
94,95,97,99,101,
104,106,108
110
111
112
113,117,119,121,
123
114
115
118,120,122
124
125
126
127
Z87001/Z87L01
ROMless Spread Spectrum Cordless Phone Controller
Table 1. 144 Pin QFP Pin Configuration
Symbol
TX
Function
Analog transmit IF signal
Direction
Output
1
AGND
Analog ground
–
RX
Analog receive IF signal
Input
AV_DD
Analog power supply
–
VREF
Analog reference voltage for RX signal
–
RFEON
RF on/off control
Output
addr[15..0]
DSP core program address bus
Output
P1[15..0]
General-purpose I/O port 1
Input/Output
GND
V_DD
idata[15..0]
Digital ground
Digital power supply
DSP core internal data bus
–
–
Output
P0[15..0]
General-purpose I/O port 0
Input/Output
data[15..0]
DSP core program data bus
Input
ANT[1..0]
TEST
HBSW
CLKOUT
VXDATA[7..0]
VXRDYB
eib
VXSTRB
iaddr[4..0]
VXRWB
trice
VXADD[2..0]
CODCLK
irwb
/RESETB
intenb
RF antenna diversity control
Test mode select
Handset/base mode select
Clock, ADPCM processor (16.384 MHz)
ADPCM processor data bus
ADPCM processor ready
External register data strobe
ADPCM processor data strobe
External register address bus
ADPCM processor read/write control
ROMless mode select
ADPCM processor address bus
Clock to codec (2.048 MHz)
External register read/write control
Master reset
Interrupt enable
Output
Input
Input
Output
Input
Output
Output
Input
Output
Input
Input
Input
Output
Output
Input
Input
DS96WRL0800
PRELIMINARY
5