Z87001 Datasheet, PDF (36/51 Pages) Zilog, Inc. – ROMless Spread Spectrum Cordless Phone Controller

Z87001/Z87L01
ROMless Spread Spectrum Cordless Phone Controller
Zilog
REGISTER DESCRIPTION (Continued)
Table 14. Bank 3 Register Description
SSPSTATE
Field
SW_SYLE
STOP_CODCLK
DBP_STOP_CLOCK
Bank 3
Bit Position
EXT2
R/W Data
f---------------
R/W 0*
1
-e--------------
R/W 0*
1
--d-------------
R/W 0*
1
BSYNC_GAIN
---c------------
R/W 0*
1
BIAS_ENABLE
----b-----------
R/W 0*
1
TX_ENABLE
-----a----------
R/W 0*
1
SYNC_SEARCH_WORD ------9---------
R/W 0*
1
SYNC_SEARCH_MODE -------87-------
R/W 00*
01
10
11
HOP_ENABLE
---------6------
R/W 0
1
SYNC_ACQ_CLEAR
----------5-----
R
W
1->0
FRAME_START_CLEAR -----------4----
R
W
1->0
SLEEP_WAKE
------------3---
R/W 0
1
MULTIPLEX_SWITCH
-------------21-
R/W 00*
01
10
11
Description
Controls accelerated synthesizer programming after sleep
Not Active
Active
Inhibits toggling of codec clock output during sleep
CODCLK is free running
CODCLK is frozen high
Controls toggling of CLKOUT output pin (clock for ADPCM
Processor).
CLKOUT is free running
CLKOUT is frozen high
Selects gain for first order loop of the bit synchronizer
Nominal gain
Gain divided by 64
Controls closed-loop AFC circuit
No new bias estimation is performed (latest estimate used)
Enables BIAS_ERROR_DATA updates
Global enable for all transmit functions
Transmitter disabled
Transmitter enabled
Controls the word searched for in search mode
Search for UW pattern (Unique Word)
Search for SYNC_D pattern
Controls the search mode (and frame synchronization)
No search
Window search (<= UW_LOCATION & WINDOW_SIZE)
Full search (during whole frame)
Not used
Enables transmission of the hop pulse on SYLE pin
Hop pulse disabled
Hop pulse enabled
Clears the SYNC_ACQ_IND flag.
Returns last value written
A transition from 1 to 0 clears the flag
Clears the FRAME_START_IND flag
Returns last value written
A transition from 1 to 0 clears the flag
Enable bit for entering sleep mode
Wake mode only
Sleep mode can be activated by GO_TO_SLEEP
command
Controls operation of the transceiver
SMUX (bit inversion and ADPCM Processor access
disabled)
STMUX (bit inv. enabled; ADPCM Proc. access disabled)
Reserved
TMUX (bit inversion and ADPCM Processor access
enabled)
36
PRELIMINARY
DS96WRL0800