Z87001 Datasheet, PDF (32/51 Pages) Zilog, Inc. – ROMless Spread Spectrum Cordless Phone Controller

Z87001/Z87L01
ROMless Spread Spectrum Cordless Phone Controller
Table 7. Data and Control Access to Rate Buffers
Field
RX_AUTO_INCREMENT
RX_BUF_ADDR
TX_AUTO_INCREMENT
TX_BUF_ADDR
RX_BUF_DATA
TX_BUF_DATA
TX_BUF_DATA
RX_BUF_VP_ADDR
TX_BUF_VP_ADDR
TX_RX_NIBBLE_MARKER
Register
RATE_BUF_ADDR
RATE_BUF_ADDR
RATE_BUF_ADDR
RATE_BUF_ADDR
RATE_BUF_DATA
RATE_BUF_ADDR
RATE_BUF_DATA
RATE_BUF_DATA
RATE_BUF_DATA
RATE_BUF_DATA
Bank
1
1
1
1
1
1
1
1
1
1
Next
EXT0
EXT0
EXT0
EXT0
EXT0
EXT1
EXT1
EXT1
EXT1
EXT1
Zilog
ADDITIONAL FEATURES
Power Control
The Z87001 features several means of measuring and
controlling power levels. One input pin (RSSI) connects an
external “receive signal strength indicator” to a half flash 8-
bit ADC in the Z87001. This ADC is sampled once per
frame during the receive portion of the TDD cycle. The
RSSI value can be accessed in software in the
RSSI_DATA register field. With external multiplexing, the
8-bit ADC can be used for additional purposes.
The RSSI data is used by the software to implement adap-
tive power control. In order to determine whether the RSSI
information is made of signal or noise, the Z87001 includes
logic to measure the signal-to-noise ratio (SNR) of the re-
ceive signal. This SNR value is available at the end of ev-
ery frame in the SNR_ESTIMATE register field. It is also
used by the adaptive frequency hopping algorithm to de-
termine and avoid the noisy channels.
Finally, a 4-bit DAC (resistive ladder) is provided to control
RF power output level. The DAC is under software control
through register field TX_PWR_DAC_DATA.
Table 8. Power Control
Field
RSSI_DATA
SNR_ESTIMATE
TX_PWR_DAC_DATA
RSSI_DATA
SNR_ESTIMATE
Register
RSSI
RX_CONTROL
CONTROL
RSSI
RX_CONTROL
Bank Ext
2 EXT3
2 EXT1
1 EXT6
2 EXT3
2 EXT3
General-Purpose I/O Ports
The Z87001 includes two general-purpose input/output
ports, P0 and P1, of 16 bit each. The direction of each bit
is independently programmable by setting the register
fields DIRECTION0 and DIRECTION1. Then, the software
can access the input and output values by accessing
DATA0 and DATA1.
Two pins of port P1 (pins 14 and 15), when configured in
input mode, also behave as interrupt pins for the core pro-
cessor. The software can enable or disable each interrupt
by setting the INTERRUPT_0_ENABLE and
INTERRUPT_2_ENABLE fields. The interrupts are posi-
tive edge-triggered.
Pin
Number
P1 14
P1 15
Interrupt
Number
INT0
INT2
DSP Interrupt
Vector
3FFFh
3FFDh
Table 9. General-Purpose I/O Ports
Field
DIRECTION0
DATA0
DIRECTION1
DATA1
INTERRUPT_0_ENABLE
INTERRUPT_1_ENABLE
Register
GPI00DIR
GPI00DATA
GPI0IDIR
GPI0IDATA
CONTROL
CONTROL
Bank
3
3
3
3
1
1
Ext
EXT4
EXT5
EXT6
EXT7
EXT6
EXT6
Four pins of port P0 (pins 0 to 3), when configured in input
mode, can also be individually programmed as wake-up
pins for the Z87001 (See “Sleep mode”, above).
32
PRELIMINARY
DS96WRL0800