Z8FS021 Datasheet, PDF (41/68 Pages) Zilog, Inc. – Select from an assortment of lenses and pyroelectric sensors to best fit your application

ZMOTION^® Intrusion Detection
Product Specification
33
Table 13. PIR Status/Control Register 3, 8-Pin SOIC
(ePIR_SC3)
Bit
7
6
5
4
3
2
1
Field
ANA3
ANA1
Reserved Reserved Reserved Reserved Scan Reserved Scan
Request
Request*
R/W
Reserved
Control
0
0
0
0
in
0
R/W
Dual Pyro
Mode
Address
105H
Note: *ANA1 is reserved for White Light detection when enabled via PIR Status/Control Register 2.
0
ANA0
Scan
Request
R/W
ANAx Scan Request
Analog Channel 0, 1, 3-7 Scan Requested Bits
Set by the application; cleared by the PIR Engine.
These bits allow the user application to request the Engine to perform an A/D conversion on the non-
reserved analog inputs. When requested, the Engine will reconfigure the appropriate I/O pin to a single-
ended, unbuffered input using a 2 Volt reference. It will then take the next sample and store it in the PIR
ADC Result Value Registers and clear all ANAx Scan Request bits. The I/O configuration for the ANAx
pin is not returned to its previous configuration by the Engine. If required, the user application must
perform this task.
If multiple request bits are set simultaneously, the Engine will only scan the lowest-numbered ADC
channel requested and ignore any other requests. The user application should set one request bit, then
poll it to determine when the conversion is complete and the data is ready.
When ADC Scan requests are being serviced by the PIR Engine, ADC conversions on the PIR sensor are
suspended. Therefore, the user application should be careful not to continuously request ADC Scans.
The PIR Process Rate Register in the Advanced API Register Set section can be monitored to ensure the
Engine is receiving enough time to perform its required PIR Sensor ADC scans.
0 = no conversion requested/last conversion completed.
1 = perform a conversion on this channel.
PS028806-0315
Standard API Register Set