Z86C03 Datasheet, PDF (317/348 Pages) Zilog, Inc. – General-Purpose Register File. Flexible I/O. Analog Inputs

Z8 CPU
User Manual
299
Flag
C
Z
S
V
D
H
Description
Set if the bit rotated from the least significant bit position was 1 (
i.e., bit 0 was 1).
Set if the result is zero; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Set if arithmetic overflow occurred (if the sign of the destination
operand changed during rotation); cleared otherwise.
Unaffected
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b (Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECh will be used as the
destination operand in the Op Code.
E
dst
Example
If the contents of Working Register R6 are 31h (00110001B), the state-
ment:
RR R6
Op Code: E0 E6
leaves the value 98h (10011000) in Working Register R6. The C, V, and
S Flags are set, and the Z Flag is cleared.
Example
If the contents of Register C6 are 31h and the contents of Register 31h
are 7Eh (01111110b), the statement:
RR @C6
Op Code: E1 C6
leaves the value 4Fh (00111111) in Register 31h. The C, Z, V, and S
flags are cleared.
UM001602-0904
Instruction Description