Z86C03 Datasheet, PDF (274/348 Pages) Zilog, Inc. – General-Purpose Register File. Flexible I/O. Analog Inputs

Z8 Family of Microcontrollers
User Manual
256
Increment Word
INCW dst
Instruction Format
OPC
OPC Address Mode
Cycles (Hex)
dst
10
A0
RR
dst
10
A1
IR
10
A0
R
Operation
dst ← dst–1
The contents of the destination (which must be an even address) operand
is decremented by one. The destination operand can be a Register Pair or
a Working Register Pair.
Flag
C
Z
S
V
D
H
Description
Unaffected
Set if the result is zero; cleared otherwise.
Set if the result of bit 7 is set (negative); cleared otherwise.
Set if arithmetic overflow occurs; cleared otherwise.
Unaffected
Unaffected
Note:
Address modes RR or IR can be used to specify a 4-bit Working Register
Pair. In this format, the destination Working Register Pair operand is spec-
ified by adding 1110b (Eh) to the high nibble of the operand. For exam-
ple, if Working Register Pair R12 (CH) is the destination operand, then
ECh will be used as the destination operand in the Op Code
E
dst
Example
If Register Pairs 30h and 31h contain the value 0AF2h, the statement:
Instruction Description
UM001602-0904