Z84C90 Datasheet, PDF (31/31 Pages) Zilog, Inc. – KIO Serial/Parallel Counter Timer

Z84C90
KIO Serial/Parallel Counter Timer
26
Work Around:
This problem could happen under the following narrowly defined conditions:
• CE signal is active throughout the Interrupt Acknowledge cycle.
• The address on the bus, A3–A0, is “110b”.
• During this time, bit D3 is 1.
• At the end of the Interrupt Acknowledge cycle, M1 goes inactive prior to the IORQ
signal.
• At the time period of CE active, IORQ active, and M1 returns to the inactive state; all
during the rising edge of the clock.
This problem is not the case with the Z80 CPU. However, other CPUs could be affected.
One of the possible workarounds is to add the condition M1 not active to generate a CE
signal.
PS011802-0902