Z84C90 Datasheet, PDF (21/31 Pages) Zilog, Inc. – KIO Serial/Parallel Counter Timer

Z84C90
KIO Serial/Parallel Counter Timer
16
Table 5. AC Characteristics of the Z84C90 (Continued)
8MHz
No. Symbol
Parameter
Min Max
22 TsIEI(Cf)
IEI to Clock Fall Setup (for 4D
50
Decode)
23 TsIOr(Cf)
IORQ Rise to Clock Fall Setup
100
(to activate RDY on next clock)
PIO Timing
24 TdCf(RDYr) Clock Fall to RDY Rise Delay
100
25 TdCf(RDYf) Clock Fall to RDY Fall Delay
100
26 TwSTB
STB Pulse Width
100
27 TsSTBr(Cf) STB Rise to Clock Fall Setup
100
(to activate RDY on next clock
cycle)
28 TdIOf(PD)
IORQ Fall to Port Data Valid
140
(Mode 0)
29 TsPD(STBr) Port A,B Data to STB Rise Setup 140
Time (Mode 1)
30 TdSTBI(PD) STB Fall to Port A,B Data Valid
150
Delay (Mode 2)
31 TdSTBr(PDz) STB Rise to Port Data Float Delay
140
(Mode 2)
32 TdPD(INTf) Port Data Match to INT Fall Delay
250
(Mode 3)
33 TdSTBr(INTf) STB Rise to INT Fall Delay
290
34 TsPD(RIf)
PIA Port Data to RD, IORQ Fall
Setup
TBD
35 TdCr(PD)
Clock Rise to Port Data Valid Delay
80
CTC Timing
36 TdCr(INTf) Clock Rise to INT Rise Delay
TcC+100
37 TsCTRr(Cr)c CLK/TRG Rise to Clock Rise Setup 90
(for immediate count, Counter
mode)
38 TsCTRr(Cr)t
CLK/TRG Rise to Clock Rise Setup 90
(for enabling prescaler on following
Clock Rise, Timer mode)
10MHz¹
12MHz
Min Max Min Max U/M
40
30
ns
100
ns
100
ns
100
ns
80
ns
100
ns
120
ns
75
ns
120
ns
120
ns
200
ns
220
ns
TBD
–
80
ns
TcC+80
ns
90
ns
90
ns
PS011802-0902