Z86C61 Datasheet, PDF (30/46 Pages) Zilog, Inc. – CMOS Z8 MICROCONTROLLER

AC CHARACTERISTICS
External I/O or Memory Read and Write Timing
Z86C61/62/96 (16 MHz)
Z86C61/62/96
Z8^® MICROCONTROLLER
No Symbol
Parameter
T_A = 0°C
to +70°C
16 MHz
Min Max
T_A = –40°C
to +105°C
16 MHz
Min Max
Units
Notes
1 TdA(AS)
2 TdAS(A)
3 TdAS(DR)
4 TwAS
5 TdAZ(DS)
Address Valid to /AS rise Delay
/AS rise to Address Float Delay
/AS rise to Read Data Req’d Valid
/AS Low Width
Address Float to /DS fall
25
35
150
40
0
25
35
150
40
0
ns [2,3]
ns [2,3]
ns [1,2,3]
ns [2,3]
ns
6 TwDSR
7 TwDSW
8 TdDSR(DR)
9 ThDR(DS)
10 TdDS(A)
/DS (Read) Low Width
/DS (Write) Low Width
/DS fall to Read Data Req’d Valid
Read Data to /DS rise Hold Time
/DS rise to Address Active Delay
135
80
75
0
50
135
80
75
0
50
ns [1,2,3]
ns [1,2,3]
ns [1,2,3]
ns [2,3]
ns [2,3]
11 TdDS(AS)
/DS rise to /AS fall Delay
35
35
ns [2,3]
12 TdR/W(AS) R//W Valid to /AS rise Delay
25
25
ns [2,3]
13 TdDS(R/W) /DS rise to R//W Not Valid
35
35
ns [2,3]
14 TdDW(DSW) Write Data Valid to /DS fall (Write) Delay 25
25
ns [2,3]
15 TdDS(DW) /DS rise to Write Data Not Valid Delay
35
35
ns [2,3]
16 TdA(DR)
17 TdAS(DS)
18 TdDM(AS)
Address Valid to Read Data Req’d Valid
/AS rise to /DS fall Delay
45
/DM Valid to /AS rise Delay
25
Notes:
[1] When using extended memory timing add 2 TpC.
[2] Timing numbers given are for minimum TpC.
[3] See clock cycle dependent characteristics table.
Number
Standard Test Load
1
All timing references use 2.0 V for a logic 1 and 0.8 V for a logic 0.
2
3
4
210
210
ns [1,2,3]
45
ns [2,3]
25
ns [2,3]
Clock Dependent Formulas
Symbol
Equation
TdA(AS)
TdAS(A)
TdAS(DR)
TwAS
0.40 TpC + 0.32
0.59 TpC – 3.25
2.83 TpC + 6.14
0.66 TpC – 1.65
6
TwDSR
2.33 TpC – 10.56
7
TwDSW
1.27 TpC + 1.67
8
TdDSR(DR)
1.97 TpC – 42.5
10
TdDS(A)
0.8 TpC
11
TdDS(AS)
0.59 TpC – 3.14
12
TdR/W(AS)
0.4 TpC
13
TdDS(R/W)
0.8 TpC – 15
14
TdDW(DSW)
0.4 TpC
15
TdDS(DW)
0.88 TpC – 19
16
TdA(DR)
4 TpC – 20
17
TdAS(DS)
0.91 TpC – 10.7
18
TdDM(AS)
0.9 TpC – 26.3
30