Z86C61 Datasheet, PDF (17/46 Pages) Zilog, Inc. – CMOS Z8 MICROCONTROLLER

Z86C61/62/96
Z8^® MICROCONTROLLER
Port 3 can be configured under software control to provide
the following control functions: handshake for Ports 0 and
2 (/DAV and RDY); four external interrupt request signals
(IRQ3-IRQ0); timer input and output signals (T_IN and T_OUT),
and Data Memory Select (/DM).
Pin
I/O
P30
IN
P31
IN
P32
IN
P33
IN
P34
OUT
P35
OUT
P36
OUT
P37
OUT
T0
T1
Notes:
HS = Handshake Signals
D = Data Available
R = Ready
CTC1
T_IN
T_OUT
Table 7. Port 3 Pin Assignments
Int.
P0 HS
P1 HS
IRQ3
IRQ2
IRQ0
D/R
IRQ1
D/R
R/D
R/D
IRQ4
IRQ5
P2 HS
UART
Ext
Serial In
D/R
DM
R/D
Serial Out
UART OPERATION
Port 3 lines P30 and P37, can be programmed as serial
I/O lines for full-duplex serial asynchronous receiver/
transmitter operation. The bit rate is controlled by the
Counter/Timer0.
The Z86C61/62/96 automatically adds a start bit and two
stop bits to transmitted data (Figure 14). Odd parity is also
available as an option. Eight data bits are always transmit-
ted, regardless of parity selection. If parity is enabled, the
eighth bit is the odd parity bit. An interrupt request (IRQ4)
is generated on all transmitted characters.
Received data must have a start bit, eight data bits and at
least one stop bit. If parity is on, bit 7 of the received data
is replaced by a parity error flag. Received characters
generate the IRQ3 interrupt request.
Note: UART function is only available in stardard timing
mode (i.e., P01M D5 = 0).
Transmitted Data (No Parity)
SP SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Eight Data Bits
Two Stop Bits
Received Data (No Parity)
SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Eight Data Bits
One Stop Bit
Transmitted Data (With Parity)
SP SP P D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Seven Data Bits
Odd Parity
Two Stop Bits
Received Data (With Parity)
SP P D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Seven Data Bits
Parity Error Flag
One Stop Bit
Figure 14. Serial Data Formats
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