Z86C61 Datasheet, PDF (23/46 Pages) Zilog, Inc. – CMOS Z8 MICROCONTROLLER

Z86C61/62/96
Z8^® MICROCONTROLLER
ROM Protect. The first 16 Kbytes of program memory is
mask programmable. A ROM protect feature prevents
“dumping” of the ROM contents by inhibiting execution of
LDC, LDCI, LDE, and LDEI instructions by external pro-
gram memory when pointing to internal memory locations.
Therefore these instructions can be used only when they
are executed from internal memory, or if they are executed
from external memory and pointing to external memory
locations.
The ROM Protect option is mask-programmable, to be
selected by the customer at the time when the ROM code
is submitted.
Stack. The Z86C61/62/96 has a 16-bit Stack Pointer (R255-
R254) used for external stack that resides anywhere in the
data memory for the ROMless mode, but only from 16384
to 65535 in the ROM mode. An 8-bit Stack Pointer (R255)
is used for the internal stack that resides within the 236
general-purpose registers (R239-R4). The high byte of the
Stack Pointer (SPH-Bit 8-15) can be used as a general
purpose register when using internal stack only.
Counter/Timers. There are two 8-bit programmable
counter/timers (T0-T1), each driven by its own 6-bit pro-
grammable prescaler. The T1 prescaler can be driven by
internal or external clock sources; however, the T0 prescaler
is driven by the internal clock only (Figure 22).
r7 r6 r5 r4
r3 r2 r1 r0
R253
(Register Pointer)
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
FF
Register Group F
F0
EF
80
7F
70
6F
60
5F
50
4F
40
3F
Specified Working
Register Group
30
2F
20
1F
Register Group 1
10
0F
Register Group 0
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
R15 to R0
R15 to R4*
00
I/O Ports
* Expanded Register Group (0) is selected
in this figure by handling bits D3 to D0
as "0" in Register R253 (RP).
R3 to R0*
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each
prescaler drives its counter, which decrements the value
(1 to 256) that has been loaded into the counter. When both
the counters and prescaler reach the end of the count, a
timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is gener-
ated.
The counter can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters can
also be programmed to stop upon reaching zero (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode).
The counter, but not the prescalers, can be read at any
time without disturbing their value or count mode. The
clock source for T1 is user-definable and can be either the
internal microprocessor clock divided-by-four, or an exter-
nal signal input through Port 3. The Timer Mode register
configures the external timer input (P31) as an external
clock, a trigger input that can be retriggerable or non-
retriggerable, or as a gate input for the internal clock. Port
3, line P36, also serves as a timer output (T_OUT) through
which T0, T1 or the internal clock can be output. The
counter/timers can be cascaded by connecting the T0
output to the input of T1.
Figure 21. Register Pointer
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