Z89165 Datasheet, PDF (3/22 Pages) Zilog, Inc. – DTAD CONTROLLERS

ZILOG
GENERAL DESCRIPTION (Continued)
P00
P01
Address
or I/O
P02
P03
(Nibble
P04
Programmable) _P05
P06
P07
P10
P11
P12
Address/Data _P13
or I/O
P14
(Byte
P15
Programmable) _P16
P17
P20
P21
I/O
P22
(Bit
P23
Programmable) ^P24
P25
P26
P27
P31
Input ^P32
P33
P34
Output ^P35
P36
P37
Port 0
Port 1
Port 2
Port 3
Timer0
Timer1
Register File
256 x 8-Bit
Z8 Core
Internal Register Bus
24 Kbytes (167)
32 Kbytes (169)
Program ROM
Internal Address Bus
Internal Data Bus
Address Bus
8K Words
DSP
Program ROM
Core
Data Bus
Peripheral Data Bus of the DSP
Peripheral
Registers
(DSP)
Mailbox
Extended
Register File
(Z8)
DIN
DENA0
DCLK
DOUT
DENA1
CODEC
Interface
RMLS
/AS
/DS
R/W
PWM
Z8 EXT.
Memory
Control
PWM
(10-Bit)
Timer3
Timer2
Port 4
Port 5
ARAM
Controller
ARAM
Control
Power
-5V
Control
OSC
Z89165/166/167/168/169
DTAD CONTROLLERS
P40
P41
P42
P43
I/O
P44
(Bit
P45 ^{Programmable)}
P46
P47
P50
I/O
P51
(Bit
P52 Programmable)
P53
Data0
Data1
Data2
Data3
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ARAM_SEL0
ARAM_SEL1
/RAS
/CAS
ARAM_R/W
ARAM_/OE
/RESET
VDD
GND
Out -5V
XTAL1
XTAL2
Z89167/168/169 Functional Block Diagram
CP96TAD0103
3