EZ801905050MOD Datasheet, PDF (28/36 Pages) Zilog, Inc. – eZ80190 Module is a compact, high-performance Ethernet module

Schematic Diagrams
eZ801905050MOD
eZ80190 Module Product Specification
23
Figures 8 through 15 present the schematics of the eZ80190 Module.
ETHIRQ
-SLEEP
-ACTIVE
ETHIRQ
-SLEEP
-ACTIVE
=
PD4
PD7
0R _R14
0603
PD6
0R _R15
0603
don't
stuff
PA[0..7]
CLK_OUT
X1
XIN
3 _{OUT OE} 1
PD[0..7]
50.000MHz, 3.3V
SG-710
R13
4k7
0603
PA[0..7]
-WR
-RD
-CS[0..3]
-WR
-RD
-CS[0..3]
-CS0 --> FLASH
-CS1 --> RAM
-CS2 --> ext. IO
-CS3 --> ETH
D[0..7]
A[0..23]
D[0..7]
A[0..23]
-BUSREQ
-BUSACK
-MREQ
CLK_OUT
-BUSREQ
-BUSACK
-MREQ
CLK_OUT
-MREQ
-WR
-RD
-CS0
-CS1
-CS2
-CS3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MREQ
WR
RD
CS0
CS1
CS2
CS3
VDD
VSS
A0
A1
A2
A3
A4
A5
A6
A7
VDD
VSS
A8
A9
A10
A11
A12
A13
U1
eZ80190
TQFP100
TEST
PC7/RI1
PC6/DCD1
PC5/DSR1
PC4/DTR1
PC3/SS1/CTS1
PC2/SCK1/RTS1
PC1/SDA1/MOSI1/RxD1
PC0/SCL1/MISO1/TxD1
VSS
VDD
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ZDA
ZCL
RESET
IORQ
INSTRD
HALT
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ZDA
ZCL
-RESET
-IOREQ
-INSTRD
-HALT
R30
don't _0R
stuff ⁰⁶⁰³
IICSDA
IICSDA
IICSCL
IICSCL
R31
0R
0603
A[0..23]
0R _R32
0603
0R _R33
0603
PA7
PA6
C18
1nF
0603
C19
1nF
0603
-NMI
D[0..7]
C20 place caps close
1nF _{to pins 97, 8, 38, 48}
0603
R4
1k
0603
Figure 8. eZ80190 Module Schematic Diagram, #1 of 9—CPU
PC[0..7]
PB[0..7]
PC[0..7]
PD[0..7]
ZDA
ZCL
PB[0..7]
-RESET
-IOREQ
-INSTRD
-HALT
-NMI
PS019101-1003
PRELIMINARY
PA[0..7]
PB[0..7]
PC[0..7]
PD[0..7]
ZDA
ZCL
-RESET
-IOREQ
-INSTRD
-HALT
-NMI
Schematic Diagrams