EZ801905050MOD Datasheet, PDF (12/36 Pages) Zilog, Inc. – eZ80190 Module is a compact, high-performance Ethernet module

eZ801905050MOD
eZ80190 Module Product Specification
7
Table 1. eZ80190 Module Peripheral Bus Connector Pin Identification* (Continued)
Pin # Symbol
Pull
Up/Down* Signal Direction Comments
46 D2
PU 4k7Ω Bidirectional
47 D3
PU 4k7Ω Bidirectional
48 D4
PU 4k7Ω Bidirectional
49 D5
PU 4k7Ω Bidirectional
50 GND
51 D7
PU 4k7Ω Bidirectional
V_SS/Ground (0 V).
52 D6
Bidirectional
53 MREQ
Bidirectional
54 IORQ
Bidirectional
55 GND
56 RD
Bidirectional
V_SS/Ground (0 V).
57 WR
Bidirectional
58 INSTRD
Output
59 BUSACK
Output
60 BUSREQ
PU 2k2Ω Input
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either V_DD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
Peripheral Bus Connector (JP1)
Figure 3 illustrates the pin layout of the 60-pin I/O Connector (JP2) of the eZ80190
Module. The eZ80^® Development Platform, however, features a 50-pin connector.
The eZ80190 Module is designed to interface pin 60 of its JP2 connector to pin 50
of the eZ80^® Development Platform’s JP2 connector so that pins 1–10 of the
eZ80190 Module overlap the edge of the eZ80^® Development Platform. Table 2
identifies the pins and their functions.
PS019101-1003
PRELIMINARY
Peripheral Bus Connector (JP1)