EZ801905050MOD Datasheet, PDF (19/36 Pages) Zilog, Inc. – eZ80190 Module is a compact, high-performance Ethernet module

eZ801905050MOD
eZ80190 Module Product Specification
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the module is required for this function. In this case, the PD6 pin is not available
for GPIO on the I/O connector.
EMAC Ports
The I/O base address is user-selectable. The EMAC is connected as an 8-bit
device.
EMAC Access
For 50MHz operation, set CS3_CTL (I/O address 0xB3) to 0xF8 (7 wait states for
I/O). CS3 is used for selecting the Ethernet MAC. By pulling JP1 pin 25 (DIS_Eth)
Low, access to the Ethernet MAC can be disabled on a per-cycle basis.
Memory
The eZ80190 offers SRAM and Flash memories and the wait states that support
memory operations, as described in this section.
Wait States
To ensure that valid data is read from or written to slower memories, a number of
wait states must be inserted into the memory or I/O access operations by the pro-
cessor. The number of wait states that are required should be added by program-
ming the chip select control registers. To calculate the minimum number of wait
states required, refer to Table 4.
Table 4. Chip Frequency to Wait State Cycle Time Calculation
MHz
20
24
40
50
Cycle Time
50.0 ns
41.7 ns
25.0 ns
20.0 ns
Static RAM
The eZ80190 features 512 KB of fast SRAM. Access speed is typically 12 ns or
faster, allowing zero-wait-state operation at 50 MHz. With the CPU at 50 MHz,
PS019101-1003
PRELIMINARY
Memory