Z86C04 Datasheet, PDF (26/34 Pages) Zilog, Inc. – CMOS 8-BIT LOW-COST 1K/2K-ROM MICROCONTROLLERS

Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Clock. The on-chip oscillator has a high-gain, parallel-res-
onant amplifier for connection to a RC, crystal, ceramic
resonator, LC, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal should be
AT cut, 12 MHz max, with a series resistance (RS) less
than or equal to 100 Ohms.
The crystal should be connected across XTAL1 and
XTAL2 using the vendor’s crystal recommended capaci-
tors (which depends on the crystal manufacturer, ceramic
resonator and PCB layout) from each pin directly to device
Ground pin 14 (Figure 16).
Note that the crystal capacitor loads should be connected
to V_SS pin 14 to reduce ground noise injection.
To use 32 KHz crystal, the 32 KHz operational mask option
must be selected, and an external resistor R must be con-
nected across XTAL1 and XTAL2.To use RC oscillator,
the RC oscillator option must be selected.
HALT Mode. This instruction turns off the internal CPU
clock but not the crystal oscillation. The counter/timers and
external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain
active. The device can be recovered by interrupts, either
externally or internally generated. An interrupt request
must be executed (enabled) to exit HALT mode. After the
interrupt service routine, the program continues from the
instruction after the HALT.
STOP Mode. This instruction turns off the internal clock
and external crystal oscillation and reduces the standby
current. The STOP mode can be released by two methods.
The first method is a RESET of the device by removing
V_CC or dropping the V_CC below V_LV. The second method
is if P27 is at a low level when the device executes the
STOP instruction. A low condition on P27 releases the
STOP mode regardless if configured for input or output.
Zilog
Program execution under both conditions begins at loca-
tion 000C (Hex). However, when P27 is used to release
the STOP mode, the I/O port mode registers are not re-
configured to their default power-on conditions. This pre-
vents any I/O, configured as output when the STOP in-
struction was executed, from glitching to an unknown
state. To use the P27 release approach with STOP mode,
use the following instruction:
LD
NOP
STOP
P2M, #1XXX XXXXB
Note: (X = dependent upon user’s application.)
In order to enter STOP or HALT mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user must execute
a NOP (opcode = FFH) immediately before the appropriate
sleep instruction, that is, as follows:
FF
NOP
; clear the pipeline
6F
STOP
; enter STOP mode
or
FF
NOP
; clear the pipeline
7F
HALT
; enter HALT mode
Watch-Dog Timer (WDT). The Watch-Dog Timer is en-
abled by instruction WDT. When the WDT is enabled, it
cannot be stopped by the instruction. With the WDT in-
struction, the WDT should be refreshed once the WDT is
enabled within every Twdt period; otherwise, the Z8 resets
itself. The WDT instruction affects the Flags accordingly: Z
= 1, S = 0, V = 0.
WDT = 5F (Hex)
C1
*
32 KHz
C2
*
XTAL1
R
XTAL2
32 KHz Crystal Clock
C1
*
C2
*
Ceramic
Resonator
or Crystal
XTAL1
C1
*
XTAL1
L
XTAL2
C2
*
LC Clock
XTAL2
XTAL1
*
XTAL2
External Clock
* ^{= Use pin 14.}
C
R
XTAL1
XTAL2
RC Clock
Figure 15. Oscillator Configuration
26
PRELIMINARY
DS97DZ80502