Z86C04 Datasheet, PDF (22/34 Pages) Zilog, Inc. – CMOS 8-BIT LOW-COST 1K/2K-ROM MICROCONTROLLERS

Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Program Memory. The Z86C04/C08 can address up to
1K/2K bytes of internal program memory (Figure 11). The
first 12 bytes of program memory are reserved for the in-
terrupt vectors. These locations contain six 16-bit vectors
that correspond to the six available interrupts. Bytes 0-
1023/2047 are on-chip mask-programmed ROM.
1023/2047
Location of
First Byte of
Instruction
Executed
After RESET 12
11
10
9
8
7
Interrupt
Vector ₆
(Lower Byte)
5
4
Interrupt
Vector ₃
(Upper Byte)
2
1
0
On-Chip
ROM
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
3FH/7FFH
0CH
0BH
0AH
09H
08H
07H
06H
05H
04H
03H
02H
01H
00H
Figure 10. Program Memory Map
Register File. The Register File consists of three I/O port
registers, 125 general-purpose registers, and 14 control
and status registers (R0, R2-R3, R4-R127, and R241-
R255, respectively; see Figure 12). Note that R254 is
available for general purpose use. The Z8 instructions can
access registers directly or indirectly through an 8-bit ad-
dress field. This allows short 4-bit register addressing us-
ing the Register Pointer. In the 4-bit mode, the register file
is divided into eight working register groups, each occupy-
ing 16 continuous locations. The Register Pointer (Figure
13) addresses the starting location of the active working-
register group. Upon power-up, the general purpose regis-
ters are undefined.
Location
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
128
127
4
3
2
1
0
Stack Pointer (Bits 7-0)
Reserved
Register Pointer
Program Control Flags
Interrupt Mask Register
Interrupt Request Register
Interrupt Priority Register
Ports 0-1 Mode
Port 3 Mode
Port 2 Mode
To Prescaler
Timer/Counter0
T1 Prescaler
Timer/Counter1
Timer Mode
Not Implemented
General Purpose
Registers
Port 3
Port 2
Reserved
Port 0
Indentifiers
SPL
RP
Flags
IMR
IRQ
IPR
P01M
P3M
P2M
PRE0
T0
PRE1
T1
TMR
P3
P2
P1
P0
Figure 11. Register File
22
PRELIMINARY
DS97DZ80502