Z86C04 Datasheet, PDF (24/34 Pages) Zilog, Inc. – CMOS 8-BIT LOW-COST 1K/2K-ROM MICROCONTROLLERS

Z86C04/C08
CMOS 8-Bit Low-Cost 1K/2K-ROM Microcontrollers
OSC
÷2 ^*
Internal
Clock
Internal Data Bus
Write
Write
Read
PRE0
Initial Value
Register
T0
Initial Value
Register
T0
Current Value
Register
6-Bit
÷4
Down
Counter
8-Bit
Down
Counter
IRQ4
Zilog
Clock
Logic
÷4
6-Bit
Down
Counter
8-Bit
Down
Counter
IRQ5
Internal Clock
Gated Clock
Triggered Clock
External Trigger
T_IN P31
PRE1
Initial Value
Register
T1
Initial Value
Register
T1
Current Value
Register
Write
Write
Read
* Note: Divide-by-two is not used in Low EMI Mode.
Internal Data Bus
Figure 13. Counter/Timers Block Diagram
Interrupts. The Z8 has six interrupts from six different
sources. These interrupts are maskable and prioritized
(Figure 15). The six sources are divided as follows: the fall-
ing edge of P31 (AN1), P32 (AN2), P33 (REF), the rising
edge of P32 (AN2), and the two counter/timers. The Inter-
rupt Mask Register globally or individually enables or dis-
ables the six interrupt requests (Table 3).
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All Z8 interrupts are
vectored through locations in program memory. When an
Interrupt machine cycle is activated, an interrupt request is
granted. This disables all subsequent interrupts, saves the
Program Counter and Status Flags, and then branches to
the program memory vector location reserved for that in-
terrupt. This memory location and the next byte contain the
16-bit starting address of the interrupt service routine for
that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt requests needs service.
Note: User must select any Z86C08 mode in Zilog’s C12
ICEBOX^™ emulator. The rising edge interrupt is not
supported on the Z86CCP00ZEM emulator.
24
PRELIMINARY
DS97DZ80502