EZ80F915050MOD Datasheet, PDF (20/34 Pages) Zilog, Inc. – eZ80F91 Module compact, high-performance Ethernet module

eZ80F915050MOD
eZ80F91 Module Product Specification
14
page 15 while reading the following discussion. Also see the eZ80F91 Product
Specification (PS0192) for further details.
Bus contention occurs when two or more devices drive a common bus. The
eZ80F91's CS0 drives the Flash CE. After the access to Flash, CS0 is driven High
a maximum of 8.8 ns after the next rising edge of the Clock (T6, Figure 4). The
Flash turn-off time (T_OD) is 25 ns, which is the time from OE or CE going High to
the Flash output drivers going into High-Z mode. In other words, after the end of
the eZ80F91 Read access to Flash, it takes 8.8 ns+25 ns = 33.8 ns before Flash
stops driving the data bus. At this point, the eZ80F91 device is already well into
the next bus cycle.
Assume that the next cycle is Memory Write. During the Memory Write cycle, Data
(output) from the eZ80F91 device is valid not later than T3 = 7.5 ns, and the Write
pulse is asserted not later than 4.5 ns after the falling edge of the Clock (14.5 ns
from the Rising edge if Clock is 50 MHz). It means that during T_CON = (33.8 ns –
7.5 ns) = 26.3 ns; two devices drive the common Data Bus—the eZ80F91 device
and Flash. In turn, data that is being written during the Write operation might be
corrupted. The part used to isolate a slow Flash data bus from a fast eZ80F91 bus
has 5.5 ns turn-off time, which reduces 25 ns part of the T_CON to 5.5 ns. As a result,
bus contention still occurs, but its duration is not 26.3 ns, as the following equation
shows:
Time of contention = (8.8ns - 7.5ns + 5.5ns) = 6.8ns
Data being written is not corrupted because the Write pulse is not yet asserted.
PS019310-0904
PRELIMINARY
Onboard Component Description