EZ80F915050MOD Datasheet, PDF (16/34 Pages) Zilog, Inc. – eZ80F91 Module compact, high-performance Ethernet module

eZ80F915050MOD
eZ80F91 Module Product Specification
10
Table 3. eZ80F91 Module I/O Connector Pin Identification* (Continued)
Pin # Symbol
Pull
Signal
Up/Down Direction
Comments
30 GND
31 PD5
Bidirectional
V_SS/Ground (0 V).
32 PD4
PD 4kΩ Bidirectional
33 PD3
Bidirectional
34 PD2
Bidirectional
35 PD1
Bidirectional
36 PD0
Bidirectional
37 TDO
Output
JTAG Data Output pin.
38 TDI/ZDA
Input
JTAG Data Input pin.
39 GND
40 TRIGOUT
Output
V_SS/Ground (0 V).
Active High trigger event indicator.
41
TCK/ZCL
PU 10KΩ Input
JTAG Input. High on reset enables ZDI mode; Low on
reset enables OCI debug.
42 TMS
PU 10KΩ Input
JTAG Test Mode Select Input.
43
RTC_V_DD
RTC supply. For proper operation of the eZ80F91
Module, this pin must be connected to the same
power source that powers the module (as is done on
the ZiLOG development platform).
44 EZ80CLK
Output
Synchronous CPU clock output.
45
I²CSCL
PU 4kΩ Bidirectional I²C Bus Clock.
46 GND
47
I²CSDA
PU 4kΩ
Bidirectional
V_SS/Ground (0 V).
I²C Data Clock.
48 GND
Power
49
FlashWE
PU 10KΩ Input
V_SS/Ground (0 V).
A Low enables a Write to external Flash memory boot
block area. If this pin is unconnected, the Flash
memory boot block area is write-protected.
50 GND
V_SS/Ground (0 V).
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either V_DD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
PS019310-0904
PRELIMINARY
Pin Description