Z32F0641MCU Datasheet, PDF (192/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
12-Bit A/D Converter
ADn.IER Interrupt Enable Register
Four interrupts are provided for ADC operations. Each interrupt can be enabled by writing 1 to the
corresponding bit in the ADn.IER register.
AD0.IER=0x4000_B028, AD1.IER=0x4000_B128
7
6
5
4
3
2
1
0
DMAIRQE
0
TRGIRQE
0
EOSIRQE
0
EOCIRQE
0
RW
RW
RW
RW
4
DMAIRQE
3
TRGIRQE
2
EOSIRQE
0
EOCIRQE
DMA done interrupt enable
0: interrupt disable
1: interrupt enable
ADC trigger conversion interrupt enable
ADC sequence conversion interrupt enable
ADC single conversion interrupt enable
PS034404-0417
PRELIMINARY
189