Z32F0641MCU Datasheet, PDF (125/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
UART
Transmitter
The transmitter’s function is to transmit data transmit. The start bit, data bits, optional parity bit, and stop bit
are serially shifted, with the least significant bit first.
The number of data bits is selected in the DLAN[1:0] field in the Un.LCR register.
The parity bit is set according to the PARITY and PEN bit field in the Un.LCR register. If the parity type is
even, the parity bit depends on the one bit sum of all data bits. For odd parity, the parity bit is the inverted sum
of all data bits.
The number of stop bits is selected in the STOPBIT field in the Un.LCR register.
An example of transmit data format is shown
Figure 12.3. Transmit Data Format Example
Inter-frame Delay Transmission
The inter-frame delay function allows the transmitter to insert an idle state on the TXD line between two
characters. The width of the idle state is defined in the WAITVAL field of the Un.IDTR register. When this field
is set to 0, zero time-delay is generated. Otherwise, the transmitter holds a high level on TXD after each
transmitted character during the number of bit periods defined in the WATIVAL field.
Figure 12.4. Inter-frame Delay Timing Diagram
Transmit Interrupt
The transmit operation generates interrupt flags. When the transmitter holding register is empty, the THRE
interrupt flag will be set. When the transmitter shifter register is empty, the TXE interrupt flag will be set. Users
can select the interrupt timing that is best for the application.
PS034404-0417
PRELIMINARY
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