Z32F0641MCU Datasheet, PDF (121/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
UART
Un.BDR Baud Rate Divisor Latch Register
The UART Baud Rate Divisor Latch Register is a 16-bit register.
15
14
13
12
11
10
9
8
7
6
U0.BDR=0x4000_8020, U1.BDR=0x4000_8120
5
4
3
2
1
0
15 BDR
0
BDR
0x0000
RW
Baud rate Divider latch value
To establish communication with the UART channel, the baud rate should be set. The baud rate for the baud
rate generator is determined using divider values from 1 to 65535 The 16 bit divider register (UnBDR) is
written for desired baud rate.The baud rate calculation formula is shown below.
BDR
=
32
𝑈𝐴𝑅𝑇_{𝑃𝐶𝐿𝐾}
× 𝐵𝑎𝑢𝑑𝑅𝑎𝑡𝑒
For a speed of 48 MHz UART_PCLK, the divider value and error rate is described in table Table 12.5.
Table 12.5 Example of Baud Rate Calculation (without BFR)
UART_PCLK=48 MHz
Baud Rate Divider
Error (%)
1200
1250
0.00%
2400
625
0.00%
4800
312
0.16%
9600
156
0.16%
19200
78
0.16%
38400
39
0.16%
57600
26
0.16%
115200
13
0.16%
PS034404-0417
PRELIMINARY
118