Z86233 Datasheet, PDF (17/18 Pages) Zilog, Inc. – CMOS Z8 8K ROM CONSUMER CONTROLLER PROCESSOR

PRECAUTIONS
Z86233/243
CP96DZ81201
(1) When in ROM Protect Mode, and executing out of
External Program Memory , instructions LDC, LDCI,
LDE, and LDEI cannot read Internal Program Memory.
When in ROM Protect Mode, and executing out of
Internal Program Memory , instructions LDC, LDCI,
LDE, and LDEI can read Internal Program Memory.
(2) The device has an oscillator-free reset for the device
pins. When the device is reset from a WDT timeout,
POR, or V_BO, the reset will force the device pins to their
reset default state even if the oscillator is not running.
(3) The Port 3 outputs are reset to High State after Reset,
except after Stop-Mode Recovery, at which the outputs
remain in the last state.
(4) Extended timing is operable.
(7) Expanded register PCON is Write Only.
(8) WDTMR is writeable only within the first 60 internal
system clocks after Reset. Afterward, the WDTMR is
write protected.
(9) Device functions down to the V_LV threshold. At
temperatures less than 25°C, the V_LV threshold will rise
to a maximum V_DD of 3.6V.
(10) Low EMI is 25 percent of standard pull-down output
driver and 25 percent of standard pull-up
output driver.
(11) There is no clock filter on Reset pin.
(12) Registers FE Hex (SPH) and FF Hex (SPL) are set to
00Hex after any reset.
(5) P0/P1/P2/P3 is Low-EMI software programmable.
(6) P0/P1/P2 is software programmable for open-drain.
(13) When Low EMI OSC is selscted (PCONReg Bit D7=0),
the output drive of /DS, /AS, and R//W will also be in low
emi mode.
(14) P01M Reg Bit D4,D3 must be set to 00Hex for Z86233.
CP96DZ81201 (8/96)
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