Z86233 Datasheet, PDF (11/18 Pages) Zilog, Inc. – CMOS Z8 8K ROM CONSUMER CONTROLLER PROCESSOR

AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Table
(SCLK/TCLK = XTAL/2)
Z86233/243
CP96DZ81201
No Symbol
1 TdA(AS)
2 TdAS(A)
Parameter
Address Valid to /AS Rise Delay
/AS Rise to Address Float Delay
T_A = 0°C to +70°C
Note [3] 12 MHz 16 MHz
V_CC Min Max Min Max
3.0 35
25
5.5 35
25
3.0 45
35
5.5 45
35
T_A = –40°C to +105°C
12 MHz 16 MHz
Min Max Min Max Units Notes
35
25
35
25
45
35
45
35
ns
[2]
ns
[2]
ns
3 TdAS(DR)
4 TwAS
/AS Rise to Read Data Req’d Valid
/AS Low Width
3.0
250
180
250
180 ns [1,2]
5.5
250
180
250
180 ns
3.0 55
40
55
40
ns
[2]
5.5 55
40
55
40
ns
5 Td
6 TwDSR
Address Float to /DS Fall
/DS (Read) Low Width
3.0 0
0
5.5 0
0
3.0 200
135
5.5 200
135
0
0
0
0
200
135
200
135
ns
ns
ns [1,2]
ns
7 TwDSW
/DS (Write) Low Width
8 TdDSR(DR) /DS Fall to Read Data Req’d Valid
3.0 110
80
5.5 110
80
3.0
150
75
5.5
150
75
110
80
110
80
150
75
150
75
ns [1,2]
ns
ns [1,2]
ns
9 ThDR(DS) Read Data to /DS Rise Hold Time
3.0 0
0
5.5 0
0
10 TdDS(A) /DS Rise to Address Active Delay
3.0 45
50
5.5 55
50
0
0
0
0
45
50
55
50
ns
[2]
ns
ns
[2]
ns
11 TdDS(AS) /DS Rise to /AS Fall Delay
12 TdR/W(AS) R//W Valid to /AS Rise Delay
3.0 30
35
5.5 45
35
3.0 45
25
5.5 45
25
30
35
45
55
45
25
45
25
ns
[2]
ns
ns
[2]
ns
13 TdDS(R/W) /DS Rise to R//W Not Valid
3.0 45
35
5.5 45
35
14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 3.0 55
25
5.5 55
25
45
35
45
35
55
25
55
25
ns
[2]
ns
ns
[2]
ns
15 TdDS(DW) /DS Rise to Write Data Not Valid Delay 3.0 45
35
45
35
ns
[2]
5.5 55
35
55
35
ns
16 TdA(DR) Address Valid to Read Data Req’d Valid 3.0
310
230
310
230 ns [1,2]
5.5
310
230
310
230 ns
17 TdAS(DS)
18 TdDI(DS)
/AS Rise to /DS Fall Delay
Data Input Setup to /DS Rise
3.0 65
45
5.5 65
45
3.0 115
60
5.5 75
60
65
45
65
45
115
60
75
60
ns
[2]
ns
ns [1,2]
ns
19 TdDM(AS) /DM Valid to /AS Rise Delay
3.0 35
30
5.5 35
30
35
30
35
30
ns
[2]
ns
Notes:
[1] When using extended memory timing add 2 TpC.
[2] Timing numbers given are for minimum TpC.
[3] The V_DD voltage specification of 3.0V guarantees 3.3V ± 0.3V, and
the V_DD voltage specification of 5.5V guarantees 5.0V ±0.5V.
Standard Test Load
All timing references use 0.7 V_CC for a logic 1 and 0.2 V_CC for a logic 0.
CP96DZ81201 (8/96)
11