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Z86233 Datasheet, PDF (14/18 Pages) Zilog, Inc. – CMOS Z8 8K ROM CONSUMER CONTROLLER PROCESSOR
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AC ELECTRICAL CHARACTERISTICS
Additional Timing Table (Divide-By-One Mode, SCLK/TCLK = XTAL)
Z86233/243
CP96DZ81201
No Symbol Parameter
Vcc
Note [6]
TA = 0°C to +70°C TA = –40°C to +105°C
4 MHz
4 MHz
Min Max
Min Max Units
1 TpC
Input Clock Period
3.0V
5.5V
2 TrC,TfC
Clock Input Rise & Fall Times
3.0V
5.5V
250 DC
250 DC
25
25
250 DC
ns
250 DC
ns
25
ns
25
ns
3 TwC
4 TwTinL
Input Clock Width
Timer Input Low Width
3.0V
125
5.5V
125
3.0V
100
5.5V
70
125
ns
125
ns
100
ns
70
ns
5 TwTinH
Timer Input High Width
3.0V
3TpC
3TpC
5.5V
3TpC
3TpC
6 TpTin
Timer Input Period
3.0V
4TpC
4TpC
5.5V
4TpC
4TpC
7 TrTin,
Timer Input Rise & Fall Timer
3.0V
100
TfTin
5.5V
100
8A TwIL
Int. Request Low Time
3.0V
100
5.5V
70
100
ns
100
ns
100
ns
70
ns
8B TwIL
Int. Request Low Time
3.0V
3TpC
3TpC
5.5V
3TpC
3TpC
9 TwIH
Int. Request Input High Time
3.0V
3TpC
3TpC
5.5V
3TpC
2TpC
10 Twsm
STOP-Mode Recovery Width Spec 3.0V
12
5.5V
12
11 Tost
Oscillator Startup Time
3.0V
5.5V
Notes:
[1] Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
[2] Interrupt request via Port 3 (P33-P31).
[3] Interrupt request via Port 3 (P30).
[4] SMR-D5 = 1, POR STOP mode delay is on.
[5] Reg. WDTMR.
[6] The VDD voltage specification of 3.0V guarantees 3.3V ± 0.3V, and
the VDD voltage specification of 5.5V guarantees 5.5V ± 0.5V.
[7] SMR D1 = 0.
[8] Maximum frequency for internal system clock is 4 MHz when
using XTAL divide-by-one mode.
[9] For RC and LC oscillator, and for oscillator driven by clock driver.
5TpC
5TpC
12
ns
12
ns
5TpC
5TpC
Notes
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,7,8]
[1,2,7,8]
[1,2,7,8]
[1,3,7,8]
[1,3,7,8]
[1,2,7,8]
[1,2,7,8]
[4,8]
[4,8]
[4,8,9]
[4,8,9]
14
CP96DZ81201 (8/96)
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