Z8F083A0128ZCOG Datasheet, PDF (11/14 Pages) Zilog, Inc. – Up to 8 KB Flash memory with in-circuit programming capability

Z8 Encore!^® F083A Series Development Kit
User Manual
8
5
D2
PA6_nT1OUT 1
2
GREEN
D3
PA7_T1OUT 1
2
YELL
D
D4
PC3_COUT 1
2
RED
VCC_33V
VCC_33V
GND
GND
R7
100
R8
100
R10
10
R9
VCC_33V
100K
NOTE 3:
Resistors R20 and R21 are not populated. See Note 2.
PA0_T0IN_JP
PA1_T0OUT_JP
C
R20 R21
20 pin footprint
U6
0
0
PB1_ANA1
PB2_ANA2
PB3_ANA3
VCC_33V
PA0_T0IN
PA1_T0OUT
GND
PA2
PA3_CTS0
PA4_RXD0
1
2
3
4
5
6
7
8
9
10
PB1/ANA1
PB2/ANA2
PB3/CLKIN/ANA3
VDD
PA0/T0IN/T0OUT/XIN/
PA1/T0OUT/XOUT
GND
PA2/DE
PA3/CTS0
PA4/RXD0
PB0/ANA0
PC3/COUT/LED
PC2/ANA6/LED
PC1ANA5/CINN/LED
PC0/ANA4/CINP/LED
DBG
RESET/PD0
PA7/T1OUT
PA6/T1IN/T1OUT
PA5/TXD0
20
19
18
17
16
15
14
13
12
11
Z8F04xA
R14
0
R18
B
1M
Y1
11
33
C19
20 MHz
R15
0
C20
NOTE 2
4
SW2
GND
TEST
R11
100
PA2
3
2
Note 1:
PB6 and PB7 are dual function pins (GPIO or Analog supply)
R12, R13, R16, and R17 are zero-ohm resistors used in
conjunction with GPIO Control Registers to select function
desired. C21, C22, and C23 are bypass capacitors that are used
for better noise rejection. U8 is an optional filter that can
be used to improve the quality of the Analog Supply. The
development board is shipped configured for Analog Supply.
Table 1 shows the configurations recommended
TABLE 1
R12 R13 R16 R17
R22 U8
C21...C23
GPIO OUT IN OUT IN IN OUT
OUT
Analog IN OUT IN OUT OUT optional IN
Supply
VCC_33V
PB0_ANA0
PC3_COUT
PC2_ANA6
PC1_ANA5
PC0_ANA4
DBG
PD0
PA7_T1OUT
PA6_nT1OUT
PA5_TXD0
GND
R12
NOTE 1:
0
U8
R13
1 _IO
IO ³
0
EMI Filter
C23
+
30uF
SENSE
C22
0.033uF C21 C10
0.033uF 0.001uF
PB2_ANA2
PB4_ANA7
PB5
PB3_ANA3
VCC_33V
PA0_T0IN
PA1_T0OUT
GND
PA3_CTS0
PA4_RXD0
PA5_TXD0
PA2
PA3_CTS0
PA4_RXD0
PA5_TXD0
R16 ₀
R17 ₀
PB7
GND
SW1
PB6
R22 ₀
PB5_JP
RESET/TEST2
JP5
1
2
HEADER 2
28 pin footprint
U5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PB2/ANA2
PB4/ANA7
PB5/Vref
PB3/ANA3/CLKIN
PB6(AVDD)
VDD
PA0/T0IN/T0OUTXIN
PA1/T0OUT/XOUT
GND
PB7(AGND)
PA2/DE
PA3/CTS0
PA4/RXD0
PA5/TXD0
PB1/ANA1
PB0/ANA0
PC3/COUT/LED
PC2/ANA6/LED
PC1/ANA5/CINN/LED
PC0/ANA4/CINP/LED
DBG
RESET/PD0
PC7/LED
PC6/LED
PA7/T1OUT
PC5/LED
PC4/LED
PA6/T1IN/T1OUT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PB1_ANA1
PB0_ANA0
PC3_COUT
PC2_ANA6
PC1_ANA5
PC0_ANA4
DBG
PD0
PC7
PC6
PA7_T1OUT
PC5
PC4
PA6_nT1OUT
Z8F04xA_28
NOTE 1:
R19 _10K
DBG
PB0_ANA0
PB1_ANA1
PB2_ANA2
PB3_ANA3
PC0_ANA4
PC1_ANA5
PC2_ANA6
PB4_ANA7
C11
0.001uF
C12
0.001uF
C13
0.001uF
C14
0.001uF
C15
0.001uF
C16
0.001uF
C17
0.001uF
C18
0.001uF
GND
J2
TABLE 2
PB0_ANA0
1
2
PB1_ANA1
3
4
Note 2: The XP supports internal, external crystal, external PB2_ANA2
5
6
Clock Mode
R14
R15
R18
C19
C20
Y1
ceramic resonator, external R/C and external CMOS drive
PB3_ANA3
7
8
Internal Only none none
none none
none none ^{clock modes. R14, R15, R18, C19, C20 and Y1 are used to}
PC0_ANA4
9
PC1_ANA5
11
10
12
support the clock mode selected. The development board is
PC2_ANA6
13
14
A Crystal
0 Ohm
0 Ohm none Yes
Yes
Yes shipped configured for external 20MHz ceramic resonator or
PB4_ANA7
15
16
Ceramic Res
0 Ohm 0 Ohm none none
none
internal clock operation. When using Internal oscilator,
Yes
pins 7 and 8 could be used as GPIO ports PA0 and PA1. To do
External CMOS none
none
none
none
none
none ^{so install R20 and R21.}
Table 2 shows the recommended clock mode configurations.
HEADER 8X2
Title
(Use PA0_T0IN
pin on JP2)
Size
B
Date:
5
4
3
2
1
If Module is plugged onto the Dev Platform the local
RS232 interface is disabled by pin 50 of JP2
JP2 _{connector 2}
PB4_ANA7
1
2
PC2_ANA6
PC1_ANA5
3
4
PC0_ANA4
PB3_ANA3
5
6
PB2_ANA2
PB1_ANA1
7
8
PB0_ANA0
VCC_33V
9
10
GND
PC4
11
12
PC5
PC7
13
14
PC6
PC3_COUT
15
16
PB5_JP
D
PA6_nT1OUT
17
18
PA0_T0IN_JP
GND
19
20
PA1_T0OUT_JP
PA7_T1OUT
21
22
PA2
23
24
25
26
27
28
PD0
29
30
GND
31
PA3_CTS0
33
PA4_RXD0
35
32
34
36
PA5_TXD0
37
38
GND
39
40
41
42
43
44
PB6
45
46
PB7
47
48
GND
49
51
-RESET
53
VCC_33V 55
50
52
-DIS_IrDA
-DIS_232
-DIS_IRDA
54
56
GND
57
58
VCC_33V 59
60
C
HEADER 30x2/SM
connector 1
for
reference
onlyJP1
1
2
3
4
-TRSTN
5
6
-F91_WE 7
GND
9
8
10 VCC_33V
A6
11
A10
13
12 A0
14 A3
GND
15
16 VCC_33V
A8
17
18 A7
A13
19
20 A9
B
A15
21
22 A14
A18
23
24 A16
A19
25
26
GND
A2
27
28
A1
A11
29
30
A12
A4
31
32
A20
A5
33
34 A17
35
36 -DIS_FLASH
A21
37
38 VCC_33V
A22
39
40 A23
-CS0
41
42 -CS1
-CS2
43
44 D0
D1
45
46 D2
D3
47
48 D4
D5
49
D7
51
50 GND
52 D6
-MREQ 53
54 -IOREQ
GND
55
-WR 57
56 -RD
58 -INSTRD
-BUSACK 59
60 -BUSREQ
HEADER 30x2/SM
A
XP 4K MDS Processor Module. Schematic.
Document Number
96C0941-001
Tuesday, March 18, 2008
Sheet
1
2
of
Rev
D
3
UM020604-0508
Figure 2. Schematic, Z8 Encore!^® F083A Series MCU Development Board