AN-202 Datasheet, PDF (6/6 Pages) Exar Corporation – USB UART BOARD DESIGN CONSIDERATIONS FOR USB COMPLIANCE

Function Description
C1, C2
R1-14
ABP1, 2
Control Bits. These are configured load the R counter.
Divide ratio of the reference divider. This ratio must be: 3 ≤ R ≤ 16383.
Antibacklash Pulse Width.
ABP2 ABP1 Pulse Width
0
0
3 ns
0
1
1.5 ns
1
0
6 ns
1
1
3 ns
T1, 2
LDP
SYNC
DLY
DB23
Test modes. These bits should be zero for normal operation.
Lock Detect Precision. A low ‘0’ three cycles occur before lock detect, high ‘1’ 5 cycles.
This bit should be ‘0’ for normal operation.
This bit should be ‘0’ for normal operation.
X = Don’t care.
3. Loading the N Counter.
Figure 7 shows the general layout for the N counter latch map. Please note that the 13-bit B counter and the 6-
bit A counter, swallow counter, and control bits work in the same way as the National Semi Conductor chip.
Except for the A counter can have 6 bits.
MSB
A B Counter Latch Map
LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 C1
Reserved
CP Gain
13-bit B Counter
6-bit A Counter
Control Bits
Figure 7
Function Description
C1, C2
A1-A6
B1- B13
G1
DB22, 23
Control Bits. These are configured load the N counter.
A Counter. A1 is the LSB and A6 is the MSB. 0 ≤ A ≤ 63.
B counter. N6 is the LSB and is the MSB. 3 ≤ B ≤ 8191. A ≤ B.
Charge Pump Gain. See the following table.
F4 (F.L. ENB) G1
Operation
0
0
CP current setting 1 is permanently used.
0
1
CP current setting 2 is permanently used.
1
0
CP current setting 1 is used.
1
1
CP current is switched to setting 2. The time spent in setting 2
is dependent on which Fastlock mode is used. Once again,
please contact Z-COMM or see Analog Devices for more about
the Fastlock modes.
X = Don’t care. The N Counter does not use these bits.
Timing the Analog Devices Chip
The Analog chip has a minimum clock pulse width high and low of 25 ns, 40 MHz. This is the rate at which data
is clocked into the 24-bit shift register. When the load enable bit goes high the data is latched in.
Page 6 of 6